1. Field
Various features relate to a substrate that includes ultra fine pitch and spacing interconnects.
2. Background
There is an ongoing need to reduce the size of integrated circuit (IC) packages and dies. However, there are many issues and problems associated with reducing the size of such IC packages and dies.
FIG. 1 illustrates an example of a substrate that includes conventional routing and/or interconnects. Specifically, FIG. 1 illustrates an example of a substrate 100 that includes a dielectric layer 102, a first interconnect 104, a second interconnect 106, a third interconnect 108, a fourth interconnect 110, a first pad 112, a first via 114, a second pad 116, a second via 118, a third pad 120, a fourth pad 122, a fifth pad 124, a sixth pad 126, a first solder resist layer 130, and a second solder resist layer 132.
The first interconnect 104, the second interconnect 106, the third interconnect 108 and the fourth interconnect 110 are embedded in the dielectric layer 102. Specifically, the first interconnect 104, the second interconnect 106, the third interconnect 108, and the fourth interconnect are embedded in a first surface (e.g., top surface) of the dielectric layer 102. As shown in FIG. 1, portions (e.g., top portions) of the first interconnect 104, the second interconnect 106, the third interconnect 108, and the fourth interconnect 110 are exposed and not covered by the dielectric layer 102.
The first pad 112 is coupled to the first via 114. The first pad 112 and the first via 114 are embedded in the dielectric layer 102. The second pad 116 is coupled to the second via 118. The second pad 116 and the second via 116 are embedded in the dielectric layer 102. The third pad 120, the fourth pad 122, the fifth pad 124, and the sixth pad 126 are on a second surface (e.g., bottom surface) of the dielectric layer 102. The third pad 120 is coupled to the first via 114. The fourth pad 122 is coupled to the second via 118.
The first solder resist layer 130 covers a portion of the first surface (e.g., top surface) of the dielectric layer 102. As shown in FIG. 1, the first solder resist layer 130 does not cover the first, second, third and fourth interconnects 104-110.
The second solder resist layer 132 covers a portions the third and fourth pads 120-122, but leaves the fifth and sixth pads 124-126 exposed.
The distance between the first, second, third and fourth interconnects 104-110 is limited to a minimum spacing due to concerns of shorting that can occur when a bump (e.g., from a die) is coupled to the interconnects 104-110 of the substrate 100. As such, under conventional routing and/or interconnects, it is not possible to further reduce the size of a substrate by providing several interconnects in a smaller space (e.g., not possible to reduce the size of a substrate by increasing the interconnect density of the substrate).
FIG. 2 illustrates another example of a substrate that includes conventional routing and/or interconnects. Specifically, FIG. 2 illustrates an example of a substrate 200 that includes a dielectric layer 202, a first interconnect 204, a second interconnect 206, a third interconnect 208, a fourth interconnect 210, a first pad 212, a first via 214, a second pad 216, a second via 218, a third pad 220, a fourth pad 222, a fifth pad 224, a sixth pad 226, a first solder resist layer 230, and a second solder resist layer 232.
The first interconnect 204, the second interconnect 206, the third interconnect 208 and the fourth interconnect 210 are on a first surface (e.g., top surface) of the dielectric layer 202. As shown in FIG. 2, portions (e.g., top and side portions) of the first interconnect 204, the second interconnect 206, the third interconnect 208, and the fourth interconnect 210 are exposed.
The first pad 212 and the second pad 216 are on the first surface (e.g., top surface) of the dielectric layer 202. The first via 214 and the second via 218 are embedded in the dielectric layer 202. The first pad 212 is coupled to the first via 214. The second pad 216 is coupled to the second via 218. The third pad 220, the fourth pad 222, the fifth pad 224, and the sixth pad 226 are on a second surface (e.g., bottom surface) of the dielectric layer 202. The third pad 220 is coupled to the first via 214. The fourth pad 222 is coupled to the second via 218.
The first solder resist layer 230 covers a portion of the first surface (e.g., top surface) of the dielectric layer 202. As shown in FIG. 2, the first solder resist layer 230 does not cover the first, second, third and fourth interconnects 204-210.
The second solder resist layer 232 covers a portions the third and fourth pads 220-222, but leaves the fifth and sixth pads 224-226 exposed.
As in the example of FIG. 1, the distance between the first, second, third and fourth interconnects 204-210 is limited to a minimum spacing due to concerns of shorting that can occur when a bump (e.g., from a die) is coupled to the interconnects 204-210 of the substrate 200. As such, under conventional routing and/or interconnects, it is not possible to further reduce the size of a substrate by providing several interconnects in a smaller space (e.g., not possible to reduce the size of a substrate by increasing the interconnect density of the substrate).
Therefore, there is need for a novel substrate that provides greater interconnect density, while avoiding shorting problems that can occur when a greater number of interconnects and/or routes are provided in a smaller area of the substrate. Ideally, such a novel substrate not only provides better interconnect spacing and/or pitch, but is easy and cost effective to produce/manufacture as well.